A Tracking PLL with an FIR Loop Filter

To stabilize the feedback loop of a PLL a lead-lag filter is used, implemented by driving the charge-pump current to a series resistor capacitor network [1]. While many designs have created the needed resistor using the resistance of an amplifier [2], and even made this resistor track the operating frequency [3], all these loops suffer from periodic noise on the control voltage caused by the small ripple current inevitable in most charge-pump designs. One alternative to using a resistor is to use a finite-impulse-response (FIR) filter to generate the needed zero. In this design, the charge-pump current is added to the integrating capacitor and then a fraction A (close to 1) is subtracted from the capacitor at a later time. The net effect is that 1-A of the charge-pump current is integrated on the capacitor, and the rest is not integrated; it acts as the linear term to stabilize the loop. The delayed charge-pump current can be generated by many methods as shown in Figure 1: (a) using two delay lines to delay the clock inputs to an additional phase-frequency detector (PFD), (b) delaying the up and down pulses from the existing PFD, and (c) delaying the charge from the second charge pump. An implementation of (c), independently conceived, is presented by Lee and Razavi [5] for wireless application. This paper explores using FIR filters for link and processor applications that use ring oscillators with small multiplication factors. In particular, we extend our previous work on adaptive-supply VCO [4] to use a FIR filter by using the topology in Figure 1a. Referring to Figure 1, the closed-loop transfer function (including loop delay D T) is